Chemical mechanical planarization ("CMP") is widely used in the microelectronics industry, particularly for local and global planarization of VLSI devices with sub-micron geometries. A typical CMP process involves polishing back built-up layers of dielectrics and conductors on integrated circuit chips during manufacture.
More particularly, a resinous polishing pad having a cellular structure is traditionally employed in conjunction with a slurry, for example a water-based slurry comprising colloidal silica particles. When pressure is applied between the polishing pad and the workpiece (e.g., silicon wafer) being polished, mechanical stresses are concentrated on the exposed edges of the adjoining cells in the cellular pad. Abrasive particles within the slurry concentrated on these edges tend to create zones of localized stress at the workpiece in the vicinity of the exposed edges of the polishing pad. This localized pressure creates mechanical strain on the chemical bonds comprising the surface being polished, rendering the chemical bonds more susceptible to chemical attack or corrosion (e.g., stress corrosion). Consequently, microscopic regions are removed from the surface being polished, enhancing planarity of the polished surface. See, for example, Arai, et al., U.S. Pat. No. 5,099,614, issued March, 1992; Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989; Karlsrud et al., U.S. Pat. No. 5,329,732, issued July, 1994; and Karlsrud et al., U.S. Pat. No. 5,498,199, issued March, 1996, for further discussion of presently known lapping and planarization techniques. By this reference, the entire disclosures of the foregoing patents are hereby incorporated herein.
Presently known polishing techniques are unsatisfactory in several regards. For example, as the size of microelectronic structures used in integrated circuits decreases to sub-half-micron levels, and as the number of microelectronic structures on current and future generation integrated circuits increases, the degree of planarity required increases dramatically. The high degree of accuracy of current lithographic techniques for smaller devices requires increasingly flatter surfaces. Presently known polishing techniques are believed to be inadequate to produce the degree of local planarity and global uniformity across the relatively large surfaces of silicon wafers used in integrated circuits, particularly for future generations.
Presently known polishing techniques are also unsatisfactory in that processes designed to produce planar, defect-free surfaces are necessarily time-consuming--involving extremely fine slurry particles in conjunction with porous pads.
Presently known polishing techniques are also unsatisfactory in that traditional polishing pads require periodic conditioning to maintain their effectiveness. As a result, batch-to-batch variations persist, and other complications of the conditioning step arise (for example, degradation of the conditioning pad itself).
Microreplicated structures are generally well known in other fields, particularly in the field of optics, where--as a result of their retroreflective properties--microreplicated films have found wide application for use in Fresnel lenses, road signs and reflectors. In addition, larger examples of such structures (on the order of 100 microns in height) have been incorporated into structured abrasive articles useful for grinding steel and other metals (see, e.g., Pieper et al., U.S. Pat. No. 5,304,223, issued Apr. 19, 1994).
In the context of chemical-mechanical planarization, regular arrays of structures (e.g., hemispheres, cubes, cylinders, and hexagons) have been formed in standard polyurethane polishing pads (see e.g. , Yu et al., U.S. Pat. No. 5,441,598, issued Aug. 15, 1995). Such structures are typically over 250 microns in height, and--due to their porosity--suffer from the same asperity variations found in other polyurethane pads.
Chemical mechanical planarization techniques and materials are thus needed which will permit a higher degree of planarization and uniformity of that planarization over the entire surface of integrated circuit structures. At the same time, more efficient techniques are needed to increase the throughput of wafers through the CMP system while reducing batch-to-batch variation.